The present invention relates to a semiconductor manufacturing apparatus and method, and, more particularly, to a nonuniform ion implantation apparatus and method capable of implanting dopant ions of different doses into different regions of a wafer.
Generally, a large number of processes are carried out to manufacture a semiconductor device, especially, a semiconductor memory device, such as a dynamic random access memory (DRAM). The processes employed may include a stack formation process, an etch process, and an ion implantation process which are carried out for each wafer. In particular, the ion implantation process accelerates dopant ions such as boron or arsenic using an electric field so that the dopant ions can be transmitted through layers present on the surface of the wafer. The electric properties of materials can be changed through the ion implanting process.
FIG. 1 is a view schematically illustrating a conventional ion implantation apparatus used to carry out an ion implantation process.
Referring to FIG. 1, a conventional ion implantation apparatus comprises a quadruple magnetic pole assembly 110, an X-directional scanner 120, a beam collimator 130, and an accelerator 140. Quadruple magnetic pole assembly 110 serves to magnify and reduce an ion beam 102 emitted from an ion beam source (not shown). Quadrupole magnetic pole assembly 110 has quadruple magnetic poles for generating magnetic fields in the areas between the four magnetic poles. Quadruple magnetic pole assembly 110 includes a first magnetic pole assembly 111 having two S and N magnetic poles and a second magnetic pole assembly 112 having two S and N magnetic poles. X-directional scanner 120 serves to orient the ion beam 102 in the X direction such that the ion beam can be uniformly irradiated on a wafer 101. Beam collimator 130 serves to collimate the optical path of ion beam 102. Accelerator 140 serves to accelerate charged particles. Accelerator 140 may be disposed before X-directional scanner 120 according to the circumstances. Ion beam 102 is irradiated on the surface of wafer 101 while ion beam 102 is oriented in the X direction by the conventional ion implantation apparatus with the above-stated construction. At this time, the wafer is moved in the Y direction such that ion implantation is performed over the entire surface of wafer 101.
FIG. 2 is a view illustrating the operation of a Y-directional scanner for scanning the wafer 101 in the Y direction.
Referring to FIG. 2, a supporting member (not shown), which is provided to support wafer 101, is connected to a Y-directional drive shaft 210. Y-directional drive shaft 210 is connected to a drive unit 220. Y-directional drive shaft 210 is moved in the Y direction by drive unit 220 as indicated by an arrow 211. As a result, wafer 101 is also moved in the Y direction. While wafer 101 is moved in the Y direction, ion beam 102 is irradiated on wafer 101 while the ion beam is oriented in the X direction, as indicated by an arrow 103. Reference numeral 104 indicates a moving trace of ion beam 102. A first ion beam detector 231 and a second ion beam detector 232 are disposed before and after the wafer 101, respectively, for detecting doses of dopant ions implanted while the ion implanting process is carried out to provide information regarding the dosage being applied.
When the ion implanting process is carried out using the conventional ion implantation apparatus described in FIGS. 1 and 2, dopant ions having the same concentration are implanted onto the entire surface of the wafer 101. However, the implantation of dopant ions having the same concentration may not be desirable, especially when taken in conjunction with other subsequent processes. Specifically, results obtained after subsequent processes are carried out such as the thickness of the stacked layer and the degree of etching may not be uniform over the entire surface of the wafer because variables in subsequent processes are not accurately controlled. As a result, process errors can occur due to unexpected or inaccurately controlled process variables.
When a gate electrode is formed, for example, the critical dimension (hereinafter referred to as “CD”) indicating the width of the gate electrode may be changed depending upon the position of the wafer. The CD of the gate electrode may be larger in the left region of the wafer while the CD of the gate electrode may be smaller in the right region of the wafer. Alternatively, the CD of the gate electrode may be larger in the right region of the wafer while the CD of the gate electrode may be smaller in the left region of the wafer. As mentioned above, this difference can occur because many variables within other processes are not accurately controlled. When the CD of the gate electrode in the left region of the wafer is larger than that of the gate electrode in the right region of the wafer, the threshold voltage of the device in the left region of the wafer is higher than that of the device in the right region of the wafer. When the CD of the gate electrode in the right region of the wafer is larger than that of the gate electrode in the left region of the wafer, on the other hand, the threshold voltage of the device in the left region of the wafer is lower than that of the device in the right region of the wafer.
The CD difference of the gate electrode depending upon the position of the wafer can cause problems as the integration level of the device is increased. When the minimum allowable CD of the gate electrode is a larger amount such as 200 nm, for example, the reduction of yield rate due to a ±10% variation in CD values may be acceptable. However, when the minimum allowable CD of the gate electrode is reduced to 100 nm or less, however, a ±10% variation in CD distribution may represent an even worse result. Consequently, for smaller allowable CD values, the CD distribution should be set to a smaller range, for example, ±5%. Despite this change, the process margin and yield rate are still reduced, which may be an obstacle for chip manufacturers.